This invention is generally applicable to any methods in the field of digital signal processing (DSP) where multiplications are utilized. Standard DSP typically involves complex multiplications (e.g., filters, discrete Fourier transforms (DFTs), frequency shifting, etc.), which can be expensive in hardware in terms of size and power consumption. For example, the brute force multiplication of two complex numbers is (a+jb)·(c+jd)=(ac−bd)+j(ad+bc), which requires four real multiplications and two real additions (where a subtraction is just the addition of a negative number). A more efficient complex multiplication in terms of real multiplications is (a+jb)·(c+jd)=[(d(a−b)+a(c−d))]+j[c(a+b)−a(c−d)] where it can be seen that the second term of the real and imaginary component is the same. Thus, this method requires only three multiplications, but five additions. This is usually a good tradeoff because of how computationally expensive multiplications are for hardware or embedded processors. However, three real multiplications are still required for each complex multiplication. To perform many DSP tasks a multiply-accumulate approach is necessary where many multiplications are followed by a sum of the results (e.g., a FIR filter). One can see that for long filters and/or long signals the number of multiplications can grow quickly. Again, all of these multiplications are very expensive in physical space (in hardware), time (in embedded processors), and power.